Difference between revisions of "Jeffersonian Engineering Corporation"

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(The F-2 "Rapier")
 
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codomo
 
{{Infobox Corporation |
 
{{Infobox Corporation |
 
subject_name=Jeffersonian Engineering Corporation (JEC) |
 
subject_name=Jeffersonian Engineering Corporation (JEC) |
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=====The F-2 "Rapier"=====
 
=====The F-2 "Rapier"=====
  
Main Article: [[Jeffersonian Engineering Corporation/F-2 "Rapier"|F-2 "Rapier"]]
+
<i>Main Article:</i> [[Jeffersonian Engineering Corporation/F-2 "Rapier"|F-2 "Rapier"]]
 +
 
 +
The F-2 is the JEC's primary air superiority fighter.
 +
 
 +
=====The F-3 "Dagger"=====
 +
 
 +
<i>Main Article:</i> [[Jeffersonian Engineering Corporation/F-3 "Dagger"|F-3 "Dagger"]]
 +
 
 +
The F-3 is the JEC's answer to the CF-18, a long range near-Mach 3 interceptor.
 +
 
 +
=====The F-4 "Flamberge"=====
 +
 
 +
<i>Main Article:</i> [[Jeffersonian Engineering Corporation/F-4 "Flamberge"|F-4 "Flamberge"]]
 +
 
 +
The F-4 is a supersonic, strike fighter.
 +
 
 +
=====The F-5 "Foil"=====
 +
 
 +
<i>Main Article:</i> [[Jeffersonian Engineering Corporation/F-5 "Foil"|F-5 "Foil"]]
 +
 
 +
The F-5 is a supersonic, VTOL multi role fighter.
  
 
====Missiles====
 
====Missiles====
Line 71: Line 92:
 
====CPUs====
 
====CPUs====
  
The JP line of processors consist of pipelines which are arranged into cores and packages.  Processes can be scheduled to a single pipeline, a full core, or even an entire processor, in a form of reverse Hyper-Threading.  The processor works with a set of customizable at manufacture, high performance decoder, that takes standard processor instruction and converts it into μops, which the pipeline can then execute.  This allows a processor to be made for a special task by merely using a different decoder instead of necessitating a whole new architecture.
+
The JP line of processors consist of pipelines which are arranged into cores and packages.  Processes can be scheduled to a single pipeline, a full core, or even an entire processor, in a form of reverse Hyper-Threading.  The processor works with a set of customizable at manufacture, high performance decoder, that takes standard processor instruction and converts it into μops, which the pipeline can then execute.  This allows a processor to be made for a special task by merely using a different decoder instead of necessitating a whole new architecture.
  
 
=====Standard=====
 
=====Standard=====
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**33 MHz bus speed
 
**33 MHz bus speed
 
**333 MHz Processor speed
 
**333 MHz Processor speed
**.25 μm (250 nm) process
+
**.25 μm (250 nm) process
 
**7 stage pipeline
 
**7 stage pipeline
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2/core: 1 MiB
 
***L2/core: 1 MiB
 
***L3/package: 8 MiB
 
***L3/package: 8 MiB
***Instruction/decoder: 1 kμops
+
***Instruction/decoder: 1 kμops
 
***Result/core: 1 MiB
 
***Result/core: 1 MiB
 
**Pentium III Rating:
 
**Pentium III Rating:
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**67 MHz bus speed
 
**67 MHz bus speed
 
**667 MHz Processor speed
 
**667 MHz Processor speed
**.18 μm (180 nm) process
+
**.18 μm (180 nm) process
 
**8 stage pipeline
 
**8 stage pipeline
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 2 MiB
 
***L2 cache/core: 2 MiB
 
***L3 cache/package: 8 MiB
 
***L3 cache/package: 8 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 2 MiB
 
***Result cache/core: 2 MiB
 
**Pentium III Rating:
 
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**100 MHz bus speed
 
**100 MHz bus speed
 
**1 GHz Processor speed
 
**1 GHz Processor speed
**.18 μm (180 nm) process
+
**.18 μm (180 nm) process
 
**8 stage pipeline
 
**8 stage pipeline
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 2 MiB
 
***L2 cache/core: 2 MiB
 
***L3 cache/package: 8 MiB
 
***L3 cache/package: 8 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 2 MiB
 
***Result cache/core: 2 MiB
 
**Pentium III Rating:
 
**Pentium III Rating:
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**250 MHz bus speed
 
**250 MHz bus speed
 
**2.5 GHz Processor speed
 
**2.5 GHz Processor speed
**.13 μm (130 nm) process
+
**.13 μm (130 nm) process
 
**13 stage pipeline
 
**13 stage pipeline
 
**6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
 
***L3 cache/package: 16 MiB
 
***L3 cache/package: 16 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
**Pentium III Rating:
 
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***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
 
***L3 cache/package: 16 MiB
 
***L3 cache/package: 16 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
**Pentium III Rating:
 
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**33 MHz bus speed
 
**33 MHz bus speed
 
**267 MHz Processor speed
 
**267 MHz Processor speed
**.25 μm (250 nm) process
+
**.25 μm (250 nm) process
 
**7 stage pipeline
 
**7 stage pipeline
 
**2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
 
**2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
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***L1/pipeline: 32 kiB
 
***L1/pipeline: 32 kiB
 
***L2/core: 1 MiB
 
***L2/core: 1 MiB
***Instruction/decoder: 1 kμops
+
***Instruction/decoder: 1 kμops
 
***Result/core: 1 MiB
 
***Result/core: 1 MiB
 
**Pentium III Rating:
 
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**67 MHz bus speed
 
**67 MHz bus speed
 
**533 MHz Processor speed
 
**533 MHz Processor speed
**.18 μm (180 nm) process
+
**.18 μm (180 nm) process
 
**8 stage pipeline
 
**8 stage pipeline
 
**2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
 
**2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
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***L1 cache/pipeline: 64 kiB
 
***L1 cache/pipeline: 64 kiB
 
***L2 cache/core: 2 MiB
 
***L2 cache/core: 2 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 2 MiB
 
***Result cache/core: 2 MiB
 
**Pentium III Rating:
 
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**100 MHz bus speed
 
**100 MHz bus speed
 
**800 MHz Processor speed
 
**800 MHz Processor speed
**.18 μm (180 nm) process
+
**.18 μm (180 nm) process
 
**8 stage pipeline
 
**8 stage pipeline
 
**2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
 
**2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
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***L1 cache/pipeline: 64 kiB
 
***L1 cache/pipeline: 64 kiB
 
***L2 cache/core: 2 MiB
 
***L2 cache/core: 2 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 2 MiB
 
***Result cache/core: 2 MiB
 
**Pentium III Rating:
 
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**250 MHz bus speed
 
**250 MHz bus speed
 
**2 GHz Processor speed
 
**2 GHz Processor speed
**.13 μm (130 nm) process
+
**.13 μm (130 nm) process
 
**13 stage pipeline
 
**13 stage pipeline
 
**3 pipelines (3 pipelines/core, 1 cores/package, 1 decoder/pipeline)
 
**3 pipelines (3 pipelines/core, 1 cores/package, 1 decoder/pipeline)
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***L1 cache/pipeline: 128 kiB
 
***L1 cache/pipeline: 128 kiB
 
***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
**Pentium III Rating:
 
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***L1 cache/pipeline: 128 kiB
 
***L1 cache/pipeline: 128 kiB
 
***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
**Pentium III Rating:
 
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**83 MHz bus speed
 
**83 MHz bus speed
 
**333 MHz Processor speed
 
**333 MHz Processor speed
**.25 μm (250 nm) process
+
**.25 μm (250 nm) process
 
**7 stage pipeline
 
**7 stage pipeline
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2/core: 1 MiB
 
***L2/core: 1 MiB
 
***L3/package: 8 MiB
 
***L3/package: 8 MiB
***Instruction/decoder: 1 kμops
+
***Instruction/decoder: 1 kμops
 
***Result/core: 1 MiB
 
***Result/core: 1 MiB
 
**Pentium III Rating:
 
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**167 MHz bus speed
 
**167 MHz bus speed
 
**667 MHz Processor speed
 
**667 MHz Processor speed
**.18 μm (180 nm) process
+
**.18 μm (180 nm) process
 
**8 stage pipeline
 
**8 stage pipeline
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 2 MiB
 
***L2 cache/core: 2 MiB
 
***L3 cache/package: 8 MiB
 
***L3 cache/package: 8 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 2 MiB
 
***Result cache/core: 2 MiB
 
**Pentium III Rating:
 
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**250 MHz bus speed
 
**250 MHz bus speed
 
**1 GHz Processor speed
 
**1 GHz Processor speed
**.18 μm (180 nm) process
+
**.18 μm (180 nm) process
 
**8 stage pipeline
 
**8 stage pipeline
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 2 MiB
 
***L2 cache/core: 2 MiB
 
***L3 cache/package: 8 MiB
 
***L3 cache/package: 8 MiB
***Instruction cache/decoder: 2 kμops
+
***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 2 MiB
 
***Result cache/core: 2 MiB
 
**Pentium III Rating:
 
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**625 MHz bus speed
 
**625 MHz bus speed
 
**2.5 GHz Processor speed
 
**2.5 GHz Processor speed
**.13 μm (130 nm) process
+
**.13 μm (130 nm) process
 
**13 stage pipeline
 
**13 stage pipeline
 
**6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
 
***L3 cache/package: 16 MiB
 
***L3 cache/package: 16 MiB
***Instruction cache/decoder: 2 kμops
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***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
**Pentium III Rating:
 
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***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
 
***L3 cache/package: 16 MiB
 
***L3 cache/package: 16 MiB
***Instruction cache/decoder: 2 kμops
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***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
**Pentium III Rating:
 
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**250 MHz bus speed
 
**250 MHz bus speed
 
**2.5 GHz Processor speed
 
**2.5 GHz Processor speed
**.13 μm (130 nm) process
+
**.13 μm (130 nm) process
 
**13 stage pipeline
 
**13 stage pipeline
 
**8 pipelines (4 pipelines/core, 2 cores/package, 1 decoder/pipeline)
 
**8 pipelines (4 pipelines/core, 2 cores/package, 1 decoder/pipeline)
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***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
 
***L3 cache/package: 16 MiB
 
***L3 cache/package: 16 MiB
***Instruction cache/decoder: 2 kμops
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***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
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***L2 cache/core: 4 MiB
 
***L2 cache/core: 4 MiB
 
***L3 cache/package: 16 MiB
 
***L3 cache/package: 16 MiB
***Instruction cache/decoder: 2 kμops
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***Instruction cache/decoder: 2 kμops
 
***Result cache/core: 4 MiB
 
***Result cache/core: 4 MiB
 
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***L2 cache/core: 8 MiB
 
***L2 cache/core: 8 MiB
 
***L3 cache/package: 64 MiB
 
***L3 cache/package: 64 MiB
***Instruction cache/decoder: 4 kμops
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***Instruction cache/decoder: 4 kμops
 
***Result cache/core: 8 MiB
 
***Result cache/core: 8 MiB
 
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***L2 cache/core: 8 MiB
 
***L2 cache/core: 8 MiB
 
***L3 cache/package: 32 MiB
 
***L3 cache/package: 32 MiB
***Instruction cache/decoder: 4 kμops
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***Instruction cache/decoder: 4 kμops
 
***Result cache/core: 8 MiB
 
***Result cache/core: 8 MiB
 
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***L2 cache/core: 8 MiB
 
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***L3 cache/package: 64 MiB
 
***L3 cache/package: 64 MiB
***Instruction cache/decoder: 4 kμops
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***Instruction cache/decoder: 4 kμops
 
***Result cache/core: 8 MiB
 
***Result cache/core: 8 MiB
 
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***L2 cache/core: 8 MiB
 
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***L3 cache/package: 96 MiB
 
***L3 cache/package: 96 MiB
***Instruction cache/decoder: 4 kμops
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***Result cache/core: 8 MiB
 
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***L2 cache/core: 8 MiB
 
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***L3 cache/package: 64 MiB
 
***L3 cache/package: 64 MiB
***Instruction cache/decoder: 4 kμops
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***Instruction cache/decoder: 4 kμops
 
***Result cache/core: 8 MiB
 
***Result cache/core: 8 MiB
 
**Pentium III Rating:
 
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Latest revision as of 22:00, 6 November 2007

codomo

Jeffersonian Engineering Corporation (JEC)
JECLogo.PNG
Headquarters: Eternos
Nationality: The Confederacy of Liberal Men and Women
Specialty: Microchips, other Computer components, munitions
Storefront: N/A

The Jeffersonian Engineering Corporation was founded by Marvin Jefferson, first president of the Confederacy, about 5 years before the breaking. The JEC dominated the computer parts market in under 3 years, and are beginning a program to remove the Cairhienen Corporation's control over the UDFCLMW.

The JEC is currently trying to win the Confederacy's contract for the next generation of fighter aircraft.

Products

Military Hardware

Fighters

The F-2 "Rapier"

Main Article: F-2 "Rapier"

The F-2 is the JEC's primary air superiority fighter.

The F-3 "Dagger"

Main Article: F-3 "Dagger"

The F-3 is the JEC's answer to the CF-18, a long range near-Mach 3 interceptor.

The F-4 "Flamberge"

Main Article: F-4 "Flamberge"

The F-4 is a supersonic, strike fighter.

The F-5 "Foil"

Main Article: F-5 "Foil"

The F-5 is a supersonic, VTOL multi role fighter.

Missiles

  • AA-1 "Arrow"
    • RADAR guided medium range missile
    • Comparable to AIM-7 Sparrow
  • AA-2 "Bolt"
    • IR guided short range missile
    • Comparable to AIM-9 Sidewinder
  • AA-3 "Longbow"
    • Long range RADAR guided missile
    • Comparable to AIM-54 Phoenix
  • AA-4 "Hydra"
    • hybrid RADAR/IR guided medium range missile
    • Uses RADAR at longer distances, and uses both closer in to overcome chaff or flares (locks on to location where both can be seen)
  • SA-1 "Flag"
    • Short Range low to medium altitude ground based anti-air missile
  • SA-2 "Beam"
    • long Range medium to high altitude ground based anti-air missile
  • SA-N-1 "Sea Flag"
    • Short Range low to medium altitude ship based based anti-air missile
  • SS-N-1 "Catapult"
    • Long range ship based cruise missile
    • Similar to BGM-109 Tomahawk
  • AS-1 "Scorpio"
    • Short range air to ground 500lb missile
  • AS-2 "Ballista"
    • Long range air to ground 2,500lb missile

Gaming Consoles

JEC Starburst

  • Main processor: JP500+ (8 pipeline)
    • Decoder capable of handling DX10, OpenGL 2.1, JGL (Jeffersonain Graphics Library) 1.5, OpenAL 1.1, JAIL (Jeffersonian Artificial Intelligence Library) 1.0
    • Meant for main system processing (running system code), controller actions, and to cover work not done by other processors (mostly handling graphics overflow)
  • Graphics Processor: 2x JP500+ (16 pipeline)
    • Decoder capable of handling DX10, OpenGL 2.1, JGL (Jeffersonain Graphics Library) 1.5, OpenAL 1.1, JAIL (Jeffersonian Artificial Intelligence Library) 1.0
    • Handles Graphics
  • CoProcessor: JP500+ (8 pipeline)
    • Decoder capable of handling DX10, OpenGL 2.1, JGL (Jeffersonain Graphics Library) 1.5, OpenAL 1.1, JAIL (Jeffersonian Artificial Intelligence Library) 1.0
    • Meant for AI, Audio, and graphics spill over
  • Main RAM: 4 GB J-D5-SDRAM
  • VRAM: 2GB each J-GRAM
  • MSRP: 300 Credits, or ~$600 equivalent

Computer Components

CPUs

The JP line of processors consist of pipelines which are arranged into cores and packages. Processes can be scheduled to a single pipeline, a full core, or even an entire processor, in a form of reverse Hyper-Threading. The processor works with a set of customizable at manufacture, high performance decoder, that takes standard processor instruction and converts it into μops, which the pipeline can then execute. This allows a processor to be made for a special task by merely using a different decoder instead of necessitating a whole new architecture.

Standard
  • JP33
    • 33 MHz bus speed
    • 333 MHz Processor speed
    • .25 μm (250 nm) process
    • 7 stage pipeline
    • 4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1/pipeline: 32 kiB
      • L2/core: 1 MiB
      • L3/package: 8 MiB
      • Instruction/decoder: 1 kμops
      • Result/core: 1 MiB
    • Pentium III Rating:
      • /pipeline: 159
      • /core: 318
      • /package: 636
  • JP66
    • 67 MHz bus speed
    • 667 MHz Processor speed
    • .18 μm (180 nm) process
    • 8 stage pipeline
    • 4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 64 kiB
      • L2 cache/core: 2 MiB
      • L3 cache/package: 8 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 2 MiB
    • Pentium III Rating:
      • /pipeline: 278
      • /core: 556
      • /package: 1,111
  • JP100
    • 100 MHz bus speed
    • 1 GHz Processor speed
    • .18 μm (180 nm) process
    • 8 stage pipeline
    • 4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 64 kiB
      • L2 cache/core: 2 MiB
      • L3 cache/package: 8 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 2 MiB
    • Pentium III Rating:
      • /pipeline: 417
      • /core: 834
      • /package: 1667
  • JP250
    • 250 MHz bus speed
    • 2.5 GHz Processor speed
    • .13 μm (130 nm) process
    • 13 stage pipeline
    • 6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • L3 cache/package: 16 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 641
      • /core: 1,923
      • /package: 3,846
  • JP500
    • 500 MHz bus speed
    • 5 GHz Processor speed
    • 65 nm process
    • 18 stage pipeline
    • 6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • L3 cache/package: 16 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 926
      • /core: 2,778
      • /package: 5,556
Mobile
  • JP33M
    • 33 MHz bus speed
    • 267 MHz Processor speed
    • .25 μm (250 nm) process
    • 7 stage pipeline
    • 2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
    • Caches
      • L1/pipeline: 32 kiB
      • L2/core: 1 MiB
      • Instruction/decoder: 1 kμops
      • Result/core: 1 MiB
    • Pentium III Rating:
      • /pipeline: 127
      • /core: 254
  • JP66M
    • 67 MHz bus speed
    • 533 MHz Processor speed
    • .18 μm (180 nm) process
    • 8 stage pipeline
    • 2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 64 kiB
      • L2 cache/core: 2 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 2 MiB
    • Pentium III Rating:
      • /pipeline: 222
      • /core: 444
  • JP100M
    • 100 MHz bus speed
    • 800 MHz Processor speed
    • .18 μm (180 nm) process
    • 8 stage pipeline
    • 2 pipelines (2 pipelines/core, 1 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 64 kiB
      • L2 cache/core: 2 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 2 MiB
    • Pentium III Rating:
      • /pipeline: 333
      • /core: 667
  • JP250M
    • 250 MHz bus speed
    • 2 GHz Processor speed
    • .13 μm (130 nm) process
    • 13 stage pipeline
    • 3 pipelines (3 pipelines/core, 1 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 513
      • /core: 1,538
  • JP500M
    • 500 MHz bus speed
    • 4 GHz Processor speed
    • 65 nm process
    • 18 stage pipeline
    • 3 pipelines (3 pipelines/core, 1 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 741
      • /core: 2,222
Super Bus
  • JP33SB
    • 83 MHz bus speed
    • 333 MHz Processor speed
    • .25 μm (250 nm) process
    • 7 stage pipeline
    • 4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1/pipeline: 32 kiB
      • L2/core: 1 MiB
      • L3/package: 8 MiB
      • Instruction/decoder: 1 kμops
      • Result/core: 1 MiB
    • Pentium III Rating:
      • /pipeline: 159
      • /core: 318
      • /package: 636
  • JP66SB
    • 167 MHz bus speed
    • 667 MHz Processor speed
    • .18 μm (180 nm) process
    • 8 stage pipeline
    • 4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 64 kiB
      • L2 cache/core: 2 MiB
      • L3 cache/package: 8 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 2 MiB
    • Pentium III Rating:
      • /pipeline: 278
      • /core: 556
      • /package: 1,111
  • JP100SB
    • 250 MHz bus speed
    • 1 GHz Processor speed
    • .18 μm (180 nm) process
    • 8 stage pipeline
    • 4 pipelines (2 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 64 kiB
      • L2 cache/core: 2 MiB
      • L3 cache/package: 8 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 2 MiB
    • Pentium III Rating:
      • /pipeline: 417
      • /core: 834
      • /package: 1667
  • JP250SB
    • 625 MHz bus speed
    • 2.5 GHz Processor speed
    • .13 μm (130 nm) process
    • 13 stage pipeline
    • 6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • L3 cache/package: 16 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 641
      • /core: 1,923
      • /package: 3,846
  • JP500SB
    • 1.25 GHz bus speed
    • 5 GHz Processor speed
    • 65 nm process
    • 18 stage pipeline
    • 6 pipelines (3 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • L3 cache/package: 16 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 926
      • /core: 2,778
      • /package: 5,556
Plus models
  • JP250+
    • 250 MHz bus speed
    • 2.5 GHz Processor speed
    • .13 μm (130 nm) process
    • 13 stage pipeline
    • 8 pipelines (4 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • L3 cache/package: 16 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 641
      • /core: 2,564
      • /package: 5,128
  • JP500+
    • 500 MHz bus speed
    • 5 GHz Processor speed
    • 65 nm process
    • 18 stage pipeline
    • 8 pipelines (4 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 128 kiB
      • L2 cache/core: 4 MiB
      • L3 cache/package: 16 MiB
      • Instruction cache/decoder: 2 kμops
      • Result cache/core: 4 MiB
    • Pentium III Rating:
      • /pipeline: 926
      • /core: 3,704
      • /package: 7,408
Experimental
  • JP1000
    • 1 GHz bus speed
    • 10 GHz Processor speed
    • 11 nm process
    • 25 stage pipeline
    • 16 pipelines (4 pipelines/core, 4 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 256 kiB
      • L2 cache/core: 8 MiB
      • L3 cache/package: 64 MiB
      • Instruction cache/decoder: 4 kμops
      • Result cache/core: 8 MiB
    • Pentium III Rating:
      • /pipeline: 1,333
      • /core: 5,333
      • /package: 21,333
  • JP1000M
    • 1 GHz bus speed
    • 8 GHz Processor speed
    • 11 nm process
    • 25 stage pipeline
    • 8 pipelines (4 pipelines/core, 2 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 256 kiB
      • L2 cache/core: 8 MiB
      • L3 cache/package: 32 MiB
      • Instruction cache/decoder: 4 kμops
      • Result cache/core: 8 MiB
    • Pentium III Rating:
      • /pipeline: 1,067
      • /core: 4,267
      • /package: 8,533
  • JP1000SB
    • 2.5 GHz bus speed
    • 10 GHz Processor speed
    • 11 nm process
    • 25 stage pipeline
    • 16 pipelines (4 pipelines/core, 4 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 256 kiB
      • L2 cache/core: 8 MiB
      • L3 cache/package: 64 MiB
      • Instruction cache/decoder: 4 kμops
      • Result cache/core: 8 MiB
    • Pentium III Rating:
      • /pipeline: 1,333
      • /core: 5,333
      • /package: 21,333
  • JP1000+
    • 1 GHz bus speed
    • 10 GHz Processor speed
    • 11 nm process
    • 25 stage pipeline
    • 24 pipelines (4 pipelines/core, 6 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 256 kiB
      • L2 cache/core: 8 MiB
      • L3 cache/package: 96 MiB
      • Instruction cache/decoder: 4 kμops
      • Result cache/core: 8 MiB
    • Pentium III Rating:
      • /pipeline: 1,333
      • /core: 5,333
      • /package: 32,000
  • JP1000M+
    • 1 GHz bus speed
    • 8 GHz Processor speed
    • 11 nm process
    • 25 stage pipeline
    • 16 pipelines (4 pipelines/core, 4 cores/package, 1 decoder/pipeline)
    • Caches
      • L1 cache/pipeline: 256 kiB
      • L2 cache/core: 8 MiB
      • L3 cache/package: 64 MiB
      • Instruction cache/decoder: 4 kμops
      • Result cache/core: 8 MiB
    • Pentium III Rating:
      • /pipeline: 1,067
      • /core: 4,267
      • /package: 17,067

GPUs

The CPUs can be retasked (by using a different decoder) as GPUs. (Ergo, any CPU can be used as a GPU)

RAM

  • J-D5-SDRAM
    • 500 MHz operation
    • Double Data Rate (Two transfers/second)
    • Bandwith:
      • On JTB @ 100 MHz: 1.5 GiB/sec
      • On JTB @ 500 MHz+: 7.5 GiB/sec
      • On JAB @ 500 MHz+: 7.5 GiB/sec
      • On JHB @ 500 MHz+: 14.9 GiB/sec
  • J-D10-SDRAM
    • 1 GHz operation
    • Double Data Rate (Two transfers/second)
    • Bandwith:
      • On JTB @ 100 MHz: 1.5 GiB/sec
      • On JTB @ 1 GHz+: 14.9 GiB/sec
      • On JAB @ 1 GHz+: 14.9 GiB/sec
      • On JHB @ 1 GHz+: 29.8 GiB/sec
  • J-Q5-SDRAM
    • 500 MHz operation
    • Quadruple Data Rate (Four transfers/second)
    • Bandwith:
      • On JTB @ 100 MHz: 3 GiB/sec
      • On JTB @ 500 MHz+: 14.9 GiB/sec
      • On JAB @ 500 MHz+: 14.9 GiB/sec
      • On JHB @ 500 MHz+: 29.8 GiB/sec
  • J-Q10-SDRAM
    • 1 GHz operation
    • Quadruple Data Rate (Four transfers/second)
    • Bandwith:
      • On JTB @ 100 MHz: 3 GiB/sec
      • On JTB @ 1 GHz+: 29.8 GiB/sec
      • On JAB @ 1 GHz+: 29.8 GiB/sec
      • On JHB @ 1 GHz+: 59.6 GiB/sec
  • J-VDORAM
    • Video RAM
    • 500 MHz operation
    • Double Data Rate (Two transfers/second)
    • Bandwith:
      • On JTB @ 100 MHz: 1.5 GiB/sec
      • On JTB @ 500 MHz+: 7.5 GiB/sec
      • On JAB @ 500 MHz+: 7.5 GiB/sec
      • On JHB @ 500 MHz+: 14.9 GiB/sec
  • J-GRAM
    • Graphics RAM
    • 1 GHz operation
    • Quadruple Data Rate (Four transfers/second)
    • Bandwith:
      • On JTB @ 100 MHz: 3 GiB/sec
      • On JTB @ 1 GHz+: 29.8 GiB/sec
      • On JAB @ 1 GHz+: 29.8 GiB/sec
      • On JHB @ 1 GHz+: 59.6 GiB/sec

Buses

  • Jeffersonian Transport Bus (JTB, 1st generation)
    • Transfers/cycled: 1
    • Bus multiplier: 1
    • Bus width: 64 bit (8 byte)
    • Bands Up/Bands Down: 2/2
    • Total Bandwith (One direction|both direction):
      • @33 MHz: 509 MiB/sec | 1,017 MiB/sec
      • @67 MHz: 1,017 MiB/sec | 2,034 MiB/sec
      • @100 MHz: 1,526 MiB/sec | 3,051 MiB/sec
      • @250 MHz: 3,815 MiB/sec | 7,629 MiB/sec
      • @500 MHz: 7,629 MiB/sec | 15,259 MiB/sec
      • @1 GHz: 15,259 MiB/sec | 30,518 MiB/sec
  • Jeffersonian Accelerated Bus (JAB, 2nd generation)
    • Transfers/cycled: 1
    • Bus multiplier: 10
    • Bus width: 64 bit (8 byte)
    • Bands Up/Bands Down: 1/1
    • Total Bandwith (One direction|both direction):
      • @33 MHz: 2.5 GiB/sec | 5 GiB/sec
      • @67 MHz: 5 GiB/sec | 10 GiB/sec
      • @100 MHz: 7.5 GiB/sec | 15 GiB/sec
      • @250 MHz: 18.75 GiB/sec | 37.5 GiB/sec
      • @500 MHz: 37.5 GiB/sec | 75 GiB/sec
      • @1 GHz: 75 GiB/sec | 150 GiB/sec
  • Jeffersonian Hyper Bus (JAB, 3rd generation)
    • Transfers/cycled: 1
    • Bus multiplier: 10
    • Bus width: 128 bit (16 byte)
    • Bands Up/Bands Down: 8/8
    • Total Bandwith (One direction|both direction):
      • @33 MHz: 39.7 GiB/sec | 79.5 GiB/sec
      • @67 MHz: 79.5 GiB/sec | 158.9 GiB/sec
      • @100 MHz: 119.2 GiB/sec | 238.4 GiB/sec
      • @250 MHz: 18.75 GiB/sec | 37.5 GiB/sec
      • @500 MHz: 298 GiB/sec | 596 GiB/sec
      • @1 GHz: 596 GiB/sec | 1.16 TiB/sec